Vhdl Two Dimensional Array Assignment In Perl

VHDL-2008: Small Changes

This page summarises a number other changes, most of which are quite small. Some of these have already been mentioned in passing on other pages, and are summarised here as well. These changes include:

  • New standard functions: minimum, maximum and to_string are defined for scalar and array types; to_bstring, to_binarystring, to_ostring, to_octalstring, to_hstring, and to_hexstring for arrays.
  • Function rising_edge is defined for type boolean.
  • Arrays and records may contain unconstrained elements.
  • These new array types are added: boolean_vector, integer_vector, real_vector, and time_vector.
  • “Matching” case statement, case?
  • force and release for signals.
  • /* */ block comments.
  • 'INSTANCE_NAME etc. extended for package and subprogram instantiation.
  • New standard environment package, ENV that includes procedures stop and finish and function resolution_limit.
  • IP encryption directives (protect) are added.

Below you'll find some more detail about the following changes:


New and changed standard functions

VHDL-2008 defines two new functions minimum and maximum. These are defined for scalar or array types.

minimum(10,11) -- returns 10 -- bv1 contains "0111" bv2 contains "1000" maximum(bv1, bv2) -- returns "1000"

Note that comparison of vectors is not done numerically unless you include an arithmetic package - the arithmetic packages overload the above functions to operate arithmetically.

Before VHDL-2008, the strength reduction functions were not defined consistently on signed, unsigned, and std_(u)logic_vector. In VHDL-2008 the following functions are now consistently defined on these types:

is_X to_X01 to_X01Z to_UX01 to_01

Array and record types

One of the main changes to composite types (array and record types) is that now you can use unconstrained array and record elements. For instance the following declarations are now legal:

type myArrayT is array (natural range <>) of std_logic_vector; type myRecordT is record a : std_logic_vector; b : std_logic_vector; end record;

The language has also been extended to allow declaration of fully or partially constrained objects and types. For instance the above record type may be used to declare a fully constrained variable as follows:

variable R : myRecordT( a(7 downto 0), b(15 downto 0) );

In certain contexts (for instance when using unconstrained ports or procedure parameters) it is possible to use the keyword open to represent a dimension that should remain unconstrained.

VHDL-2008 adds a number of new predefined array types as follows:

type boolean_vector is array (natural range <>) of boolean type integer_vector is array (natural range <>) of integer type real_vector is array (natural range <>) of real type time_vector is array (natural range <>) of time

The matching case statement

There is a new version of case which allows don't care behaviour, case?. Here is an example:

case? sel is when "1---" => o <= "11"; when "01--" => o <= "10"; when "001-" => o <= "01"; when "0001" => o <= "00"; when others => null; end case;

The comparison is carried out using the matching equality operator ?= which means that the don't care character '-' is truly treated as don't care, and also that (for instance) 'H' matches '1'. As for a regular case statement, each value of the expression at the top must be represented exactly once amongst the set of choices: when using pattern matching, you have to be careful that patterns that include the '-' do not overlap.

Forcing and releasing signals

For verification, it is sometimes convenient to be able to "override" the value of a signal. This can be used for error injection, for instance. Of course this is always possible using vendor-specific commands, typically written in Tcl. But VHDL-2008 allows this in pure VHDL.

It is also possible to remove the overridden value using the release keyword.

Finally it is possible to make a distinction between the effective and driving value of a signal (there are restrictions on ports depending on their mode).

<< tb.uut.s >> <= force '1'; -- inject error << tb.uut.s >> <= release; -- stop overriding v <= force in '1'; -- force effective value v <= force out '0'; -- force driving value v <= release in; -- release effective value v <= release out; -- release driving value

With VHDL-2008 it is now possible to achieve the same confusing errors you can with a language like C, and comment out a big chunk of code by accident, with a delimited (block) comment. (Can you tell I'm not a big fan?).

/* s <= 1; r <= 2; */

Changes to 'INSTANCE_NAME

Both 'INSTANCE_NAME and 'PATH_NAME have been corrected so that they cope with shared variables of protected type (introduced in VHDL 2000), and overloaded operators. Previously the paths and instance strings produced by these attributes did not include operator names and shared variables.

Standard environment package

An additional environment package is added. This package allows VHDL code to control the simulator, and to find out the simulator time resolution. The package is std.env.

procedure stop(status:integer); prodedure stop; procedure finish(status:integer); procedure finish; function resolution_limit return delay_length;

stop causes a simulation to stop but not to quit. finish causes a simulation to quit. The resolution_limit function allows the user to find out the simulator resolution limit - for instance you could wait for a minimum time step using

wait for env.resolution_limit;

IP Encryption

VHDL-2008 has a means of specifying that a block of data is encrypted. This uses an additional feature - the tool directive. Tool directives are arbitrary words preceded by a backtick character `. The idea of tool directives is that they are interpreted by tools, they don't have any meaning to a VHDL compiler.

For IP encryption, a set of predefined tool directives is defined as follows:

`protect begin `protect end `protect begin_protected `protect end_protected `protect author `protect author_info `protect encrypt_agent `protect encrypt_agent_info `protect key_keyowner `protect key_keyname `protect key_method `protect key_block `protect data_keyowner `protect data_keyname `portect data_method `protect data_block `protect digest_keyowner `protect digest_keyname `protect digest_key_method `protect digest_method `protect digest_block `protect encoding `protect viewport `protect decrypt_license `protect runtime_license `protect comment

Many of these tool directives have additional parameter values.

Here's a short example of what some VHDL code might look like using IP encryption:

entity e is -- ports omitted end entity; architecture RTL of e is `protect data_keyowner = "Doulos User" `protect data_keyname = "Doulos Key" `protect data_method = "rsa" `protect encoding = (enctype= "quoted-printable") `protect begin -- code omitted begin -- code omitted `protect end end architecture RTL;

Previous

Go back to the main VHDL-2008 page.

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SystemVerilog Data Types

This tutorial describes the new data types that Systemverilog introduces. Most of these are synthesisable, and should make RTL descriptions easier to write and understand.

Integer and Real Types

SystemVerilog introduces several new data types. Many of these will be familiar to C programmers. The idea is that algorithms modelled in C can more easiliy be converted to SystemVerilog if the two languages have the same data types.

Verilog’s variable types are four-state: each bit is 0,1,X or Z. SystemVerilog introduces new two-state data types, where each bit is 0 or 1 only. You would use these when you do not need X and Z values, for example in test benches and as for-loop variables. Using two-state variables in RTL models may enable simulators to be more efficient. Used appropriately, they should not affect the synthesis results.

TypeDescriptionExample
bituser-defined sizebit [3:0] a_nibble;
byte8 bits, signedbyte a, b;
shortint16 bits, signedshortint c, d;
int32 bits, signedint i,j;
longint64 bits, signedlongint lword;
Two-state integer types

Note that, unlike in C, SystemVerilog specifies the number of bits for the fixed-width types.

TypeDescriptionExample
reguser-defined sizereg [7:0] a_byte;
logicidentical to reg in every waylogic [7:0] a_byte;
integer32 bits, signedinteger i, j, k;
Four-state integer types

logic is a better name than reg, so is preferred. As we shall see, you can use logic where in the past you have may have used reg or where you may have used wire.

TypeDescriptionExample
time64-bit unsignedtime now;
shortreallike float in Cshortreal f;
reallike double in Cdouble g;
realtimeidentical to realrealtime now;
Non-integer types

Arrays

In Verilog-1995, you could define scalar and vector nets and variables. You could also define memory arrays, which are one-dimensional arrays of a variable type. Verilog-2001 allowed multi-dimensioned arrays of both nets and variables, and removed some of the restrictions on memory array usage.

SystemVerilog takes this a stage further and refines the concept of arrays and permits more operations on arrays.

In SystemVerilog, arrays may have either packed or unpacked dimensions, or both. Consider this example:

reg [3:0][7:0] register [0:9];

The packed dimensions are [3:0] and [7:0]. The unpacked dimension is [0:9]. (You can have as many packed and unpacked dimensions as you like.)

Packed dimensions:

  • are guaranteed to be laid out contiguously in memory
  • can be copied on to any other packed object
  • can be sliced ("part-selects")
  • are restricted to the "bit" types (bit, logic, int etc.), some of which (e.g. int) have a fixed size.

By contrast, unpacked dimensions can be arranged in memory in any way that the simulator chooses. You can reliably copy an array on to another array of the same type. For arrays with different types, you must use a cast, and there are rules for how an unpacked type is cast to a packed type. Unpacked arrays can be any type, such as arrays of reals.

SystemVerilog permits a number of operations on complete unpacked arrays and slices of unpacked arrays. For these, the arrays or slices involved must have the same type and the same shape – i.e. exactly the same number and lengths of unpacked dimensions. The packed dimensions may be different, as long as the array or slice elements have the same number of bits.

The permitted operations are:

  • Reading and writing the whole array
  • Reading and writing array slices
  • Reading and writing array elements
  • Equality relations on arrays, slices and elements

SystemVerilog also includes dynamic arrays (the number of elements may change during simulation) and associative arrays (which have a non-contiguous range).

To support all these array types, SystemVerilog includes a number of array querying functions and methods. For example, you could use $dimensions to find the number dimensions of an array variable.

Typedef

SystemVerilog’s data type system allows you to define quite complex types. To make this kind of code clear, the typedef facility was introduced. Typedef allows users to create their own names for type definitions that they will use frequently in their code. Typedefs can be very convenient when building up complicated array definitions.

typedef reg [7:0] octet;
octet b;

is the same as

reg [7:0] b;

and

typedef octet [3:0]
quadOctet;
quadOctet qBytes [1:10];

is the same as

reg [3:0][7:0] qBytes [1:10];

Enum

SystemVerilog also introduces enumerated types, for example

enum { circle, ellipse, freeform } c;

Enumerations allow you to define a data type whose values have names. Such data types are appropriate and useful for representing state values, opcodes and other such non-numeric or symbolic data.

Typedef is commonly used together with enum, like this:

typedef enum { circle, ellipse, freeform } ClosedCurve;
ClosedCurve c;

The named values of an enumeration type act like constants. The default type is int. You can copy them to and from variables of the enumeration type, compare them with one another and so on. Enumerations are strongly typed. You can’t copy a numeric value into a variable of enumeration type, unless you use a type-cast:

c = 2; // ERROR
c = ClosedCurve'(2); // Casting – okay

However, when you use an enumeration in an expression, the value you are working with is the literal’s integer equivalent; so, for example, it’s okay to compare an enumeration variable with an integer; and it’s okay to use an enumeration value in an integer expression.

Stuct and Union

Finally, SystemVerilog introduces struct and union data types, similar to those in C.

struct {
int x, y;
} p;

Struct members are selected using the .name syntax:

p.x = 1;

Structure literals and expressions may be formed using braces.

p = {1,2};

It is often useful to declare a new structure type using typedef and then declare variables using the new type. Note also that structs may be packed.

typedef struct packed {
int x, y;
} Point;
Point p;

Unions are useful where the same hardware resources (like a register) can store values of different types (e.g. integer, floating point, …)

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